Schedule for CSCI 351 Intro to Computer Systems

Fall 2015

Last update: 29 Sep

DateReading
Aug 26Review and introduction; historical background
28ch. 1, 2.1Memory I: Representation
context; bits, etc.; integers
312.2-3signs, arithmeticstart L0 warm-up (due Sep 9)
Sep 2finish integers and arithmeticstart L1 bits (due Sep 18)
42.4-5floating-point
7Labor Day
9Moore
3.1-4
Processor and Programs I
basic architecture, operands
L0 warm-up due
113.5, 3.8-9primitive operations, structures in memory
143.6control structuresstart L2 bomb (due Sep 30)
163.7functions
183.10-jumps, conditionsL1 bits due
213.10-loops, switch, proc. call
23Memory II: Allocation
address space
25procedure call; stacks
289.11heapsstart L3 buffer (due Oct 16)
30System Model I: Protection and Abstraction
basics of input/output
L2 bomb due
Oct 2Review
5Exam
7to be determined
98.1interrupts and exceptions, handlers
128.2
8.3-5, 8.7
process, kernel; system call
process management
146.1, 10.1-3System Model II: I/O
files, file descriptors
1610.4-reusing the fd abstractionstart L4 shell (due Nov 2)
L3 buffer due
19Quad break
219.1-2, 6.2-3Memory III: Caches and Translation
Address spaces, caches
236.4Cache organization
266.5-Cache consequencesstart L5 cache (due Nov 11)
28pragmatics
309.3-9.6Address translation
Nov 29.9-10Memory IV: Allocators
data structures
L4 shell due
4
6
9Exam
1112.3-4System Model III: Concurrency
Threads
start L6 network (due Nov 23)
L5 cache due
13
16
1811.1-4System Model IV: Networks
addressing, sockets
2011.5-RPCs
23Processors II: Parallelism
Multiprocessors
start L7 perf. (due Dec 9)
L6 network due
25-27Thanksgiving
30memory consistency
Dec 2Instruction-level parallelism
4start ch. 5code improvement (optimization)
7performance
9What lies ahead?L7 perf. due
11Review
8:00-10:00 a.m., Tues 15 DecFinal exam